This invention relates to digital signal processing for radar and communications using phase code modulation, and in particular to an apparatus and method for correlating Binary Phase-Shift Keying (BPSK) pseudo-random noise (PN) codes in a signal processor of a Global Positioning System (GPS) receiver.
Phase code modulation is ideally suited to measuring time or time delay. The time delay is a measure of range while the difference in phase measurements taken at fixed time intervals is a measure of frequency. The phase code modulation is compared (correlated) with the expected phase or replica of the phase code modulation. Typical phase code modulations include not only Binary Phase-Shift Keying (BPSK), but also Binary Frequency-Shift Keying (BFSK).
The Global Positioning System (GPS) is a navigation system based on eighteen satellites in orbit. When fully operational the eighteen satellites will be evenly dispersed in three, inclined, 12-hour circular orbits chosen to ensure continuous 24-hour coverage. The GPS will provide extremely accurate time and three-dimensional position and velocity information to users anywhere in the world. Normally, four satellites are required for precise location determinmination in four dimensions (latitude, longitude, altitude and time). The location determinations are based on measurement of the transit time of RF signals from the satellites selected from the total of eighteen. Each satellite transmits a different pair of L-band carrier signals including an L1 signal at 1575.42 MHz and an L2 signal at 1227.6 MHz. The L1 and L2 signals are biphase modulated by two pseudo-random noise (PN) codes comprising a P-code which provides for precision measurement of transit time and a C/A (course/acquisition) code which provides for a course measurement of transit time and provides for easy lock-on to the desired signal suitable for many commercial purposes. Since each satellite uses different PN-codes, a signal transmitted by a particular satellite can be selected by generating and matching (correlating) the corresponding PN-code pattern.
The P-code is the principal navigation pseudo-random noise (PN) ranging code of the Global Positioning System. The P-code is a repetitive sequence of bits referred to as chips (in spread spectrum parlance). The P-code for each satellite is the product of two PN-codes X1 and X2 where X1 has a period of 1.5 sec or 15,345,000 chips and X2 has a period of 15,345,037 or 37 chips longer. The P-code generator in a GPS receiver reproduces a replica of the P-code that is generated by a P-code generator of a particular GPS satellite and each satellite produces a unique P-code. The C/A code is a relatively short code of 1023 bits or 1 msec duration at a 1.023 Mbps bit rate. This code is selected to provide good multiple access properties for its period.
An all-digital GPS receiver is described in a paper entitled "All-Digital GPS Receiver Mechanization", by Peter C. Ould and Robert J. Van Wechel, reprinted by the Institute of Navigation, Global Positioning System Papers published in Navigation, Vol. 2, pp. 25-35, (also presented at ION Aerospace Meeting, April, 1981). Code correlation is accomplished digitally using either digital matched filters (DMF) or digital correlators, depending upon performance requirements. In particular, a correlator is described that is a three-sample, 2-bit correlator used for both C/A and P-codes wherein the quantized samples are scaled to produce all positive values so that simple up/down counters can be used to integrate the most significant bit (MSB) and least significant bit (LSB) independently. However, this approach requires one correlator/integrator in the signal processor of the GPS receiver for each analog-to-digital bit. In a subsequent paper entitled "All-Digital GPS Receiver Mechanization-Six Years Later by J. S. Graham, P. C. Ould and R. J. Van Wechel, Journal of Institute of Navigation, National Technical Meeting, January 1987, a multi-tap correlator/integrator is described that is predominantly a set of N times Y 16-bit up/down counters where N is the number of A/D bits and Y is the multiple number of taps. When sampled signals are correlated against a replica of the transmitted code, the counters count up or down to indicate a match or mismatch, respectively for each A/D bit. At the end of the correlation time interval the counts for each A/D bit are stored in holding registers accessible by a microprocessor bus. This integrate and dump function which is the optimal filter requires weighting of each 16-bit up/down counter output. The N 16-bit output weighted words are accumulated for detection of pseudo-random noise code buried in Gaussian noise. However, these approaches for pseudo-random noise code correlation result in considerable hardware even when implemented with VLSI circuitry.
New applications of the GPS system have identified the need for a GPS receiver having a signal processor implemented on a very large scale integrated (VLSI) circuit. In order to accomplish this level of integration, the signal processor has to be designed with minimum circuitry to facilitate implementing it on a VLSI circuit.